This application incorporates by reference Taiwanese application Serial No. 90100656, filed on Jan. 11, 2001.
1. Field of Invention
The invention relates in general to a detecting device, and more particularly to a phase-detecting device for a delay locked loop (DLL).
2. Description of related art
In order to meet design requirements, signals are delayed in logic circuits. Of various designs of delay circuits, delay locked loop can accurately delay input signals by xc2xc, xc2xd or one cycle to meet different requirements for different circuit designs.
FIG. 1 illustrates phase relationship between a reference signal and a delay signal. As shown, the reference signal S is a typical square wave, and the delay signal SD lags the reference signal S by xc2xc cycle (T/4). Therefore, the delay signal SD and the reference signal S have the same waveform, but their phases are different by T/4.
FIG. 2 illustrates a block diagram of a delay locked loop. The delay locked loop includes a delay circuit 210, a phase detector 220 and a counter 230, and is used for delaying a reference signal 20. As shown, the delay circuit 210 has the reference signal 20 as input, and determines a delay time based upon a counting signal 23 from the counter 230. Namely, different delay times for the reference signal 20 can be made by different counting signals 23. For example, if the counting signal 23 is 0, the delay time generated by the delay circuit 210 is shortest. By gradually increasing the value of the counting signal 23, the delay time is increased gradually, resulting in the time delay of the reference signal 20.
To further improve the accuracy of the time delay, a feedback loop is implemented. Practically, the counting signal 23 is set to 0 at the beginning such that the reference signal 20 is delayed by a shortest delay time. The delayed reference signal 20 is feedback to the phase detector 220 for detecting a phase difference between the reference signal 20 and the feedback signal 25. Accordingly, the phase detector 220 can determine whether the delay time for the reference signal 20 satisfies the design requirements. According to the detected result, the phase detector 220 feeds a delay control signal 22 into the counter 230 so that the value of the counting signal 23 is increased. The counting signal 23 is then fed into the delay circuit 210 so as to increase the delay time of the reference signal 20. As the delay time is increased, the delayed reference signal 20 is further feedback to the phase detector 220. The delay time is continuously adjusted until the delay circuit 210 generates a required delay time. Therefore, the required delay time for the reference signal 20 can be obtained.
In addition, with the circuit structure based on the circuit in FIG. 2, an approach to the obtaining of a signal at a frequency of 100 MHz with a delay time of xc2xc cycle is described as follows. That is, a signal with a delay time of 2.5 ns is to be generated according to the approach described above. FIG. 3 shows a block diagram of the delay locked loop. First, a reference signal 30 with a frequency of 200 MHz is used for delaying and adjusting. The reference signal 30 is inverted to a reference signal 30a by an inversion logic circuit 310, and then the inverted reference signal 30a is feedback to the phase detector 220. Through a buffer 320, a feedback signal 35 is buffered as a feedback signal 35a and then feedback to the phase detector 220. According to a phase difference between the feedback signal 35a and the reference signal 30a, the phase detector 220 generates a delay control signal 32 and outputs it to the counter 230 for adjusting a delay time for the reference signal 30 until the delay circuit 210 generates a correct delay time. Since the process has been explained previously, the detailed description will not be made for the sake of brevity. A timing diagram is shown next for further describing timing relationship among the signals.
FIG. 4 shows a timing diagram of the reference signal and the feedback signal in FIG. 3. Referring FIGS. 3 and 4, the reference signal 30a and the feedback signal 35a are inputted to the phase detector 220 at the same time. Because the feedback signal 35 is generated by delaying the reference signal 30 through the delay circuit 210, the phase of the feedback signal 35a lags behind the phase of the reference signal 30a, assuming the response times for both of the inversion logic circuit 310 and the buffer 320 are equal. The phase detector 220 captures the level (voltage amplitude) of the feedback signal 35a at the rising edge r0 of the reference signal 30a. For the waveforms shown in FIG. 4, the feedback signal 35a captured is a logic xe2x80x9c1xe2x80x9d. By proper design, the delay control signal 32 can be set to a logic xe2x80x9c1xe2x80x9d when the phase detector 220 captures a logic xe2x80x9c1xe2x80x9d signal. The delay control signal 32 is inputted to the counter 230 to increase the counting value of the counting signal 33; thereby, the delay time for the reference signal is extended. Accordingly, the phase difference between the feedback signal 35a and the reference signal 30a is increased as the delay time for the reference signal 30 is increased. According to the phase difference between the feedback signal 35a and the reference signal 30a, the rising edge r5 of the feedback signal 35a is shifted to right. Next, the phase detector 220 further detects the level of the feedback signal 35a at the rising edge r0 of the reference signal 30a. If the captured signal is in a logic xe2x80x9c1xe2x80x9d state, the delay control signal 32 is set to the logic xe2x80x9c1xe2x80x9d state again to increase the counting value of the counting signal 33, whereby the delay time for the reference signal 30 is further delayed. Therefore, the phase difference between the feedback signal 35a and the reference signal 30a is increased further. Namely, the rising edge r5 of the feedback signal 35a is shifted to right further. Accordingly, by the control scheme above, once the rising edge of the reference signal 30a is detected to be the logic xe2x80x9c1xe2x80x9d state, the delay time for the reference signal 30 is increased further and the feedback signal 35 is lagged behind the reference signal 30.
As the foregoing description, the rising edge of the feedback signal is gradually shifted to right as the delay time for the reference signal is gradually increased. As the rising edge of the feedback signal is further shifted to right until the rising edge r5xe2x80x2 (shown in FIG. 4) slightly lags behind the rising edge r0, the signal detected at the rising edge r0 is a logic xe2x80x9c0xe2x80x9d instead of logic xe2x80x9c1xe2x80x9d. By proper design, when the signal with the logic xe2x80x9c0xe2x80x9d state detected by the phase detector 220, the delay control signal 32 can be set to logic xe2x80x9c0xe2x80x9d. The counting value of the counting signal 33 is then decreased so that the delay time generated by the delay circuit 210 is decreased. As a result, the rising edge r5 leads the rising edge r0 so that the delay control signal 32 becomes logic xe2x80x9c1xe2x80x9d and the counting value of the counting signal 33 is increased. By repeating the foregoing process, the rising edges r0 and r5 are kept within a very short interval. As shown, the rising edges r0 and r5xe2x80x2 are apart by about xc2xd cycle.
According to the foregoing description, the delay time can be fixed at about xc2xd cycle (T/2) by the delay locked loop. Namely, when the frequency of the reference signal 30 is 200 MHz, the delay time is 2.5 ns. It should be noted that according to the original purpose it intends to delay a signal with a frequency of 100 MHz by T/4. However, in practice, the reference signal 30 with a frequency of 200 MHz is delayed to obtain a delay time of 2.5 ns. Once the delay time is determined, the delay time of 2.5 ns is equivalent to the case when a signal with a frequency of 100 MHz is delayed by T/4. Therefore, if a signal with a frequency of 100 MHz is inputted to the delay circuit 210, the signal will be delayed by T/4, which meets the design requirement. Moreover, the delay locked loop has a save lock range SR. That is, as the feedback signal 35a is within the save lock range SR, the phase lock can be completed by the phase detector 220 and the delay time can be properly obtained.
FIG. 5 shows a block diagram of a delay locked loop for generating a delay time of one cycle. The delay locked loop comprises a delay circuit 210, a phase detector 220 and a counter 230. According to a reference signal 50 and a feedback signal 55, the phase detector 220 outputs a delay control signal 52 to the counter 230 to adjust the counting value of a counting signal 53; thereby, the delay circuit 210 generates the feedback signal 55 with a required delay time. The delay process is discussed in detail as follows.
FIG. 6 shows a timing diagram of the reference 50 and the feedback signal 55 in FIG. 5. Referring to FIGS. 5 and 6, the reference signal 50 and the feedback signal 55 are inputted to the phase detector 220 at the same time. Since the feedback signal 55 is generated by delaying the reference signal 50 through the delay circuit 210, the phase of the feedback signal 55 lags behind the phase of the reference signal 50. Similarly, using the rising edge r50 of the reference signal 50, the phase detector 220 detects the status of the feedback signal 55 so as to adjust a delay time. As shown in FIG. 6, since the feedback signal 55 lags behind the reference signal 50, the phase detector 220 detects that the feedback signal 55 is in a logic xe2x80x9c0xe2x80x9d state. According to the foregoing description, when a logic xe2x80x9c0xe2x80x9d state is detected by the phase detector 220, the counting value of the counting signal 33 is decreased. If the counting signal 33 reaches its minimum value at the beginning, the delay time of the feedback signal 55 generated by the delay circuit 210 is kept and not changed. Therefore, the reference signal 50 cannot be delayed by one cycle. The delay locked loop has a failure phase-lock range FR. Namely, once the feedback signal 55 is within the FR range, the objective of phase locking cannot be achieved and the circuit cannot function properly.
Accordingly, the drawback of the conventional circuit configuration is that it has to provide two different delay locked loops for providing two different delay cycles, such as T/4 and 1T. It is impossible to provide two different delay times using the same delay locked loop. Therefore, the occupied circuit area is doubled, and cost and complexity are increased.
This invention provides a phase detecting device having a phase lock loop capable of providing different delay times, such as T/4, T/2 and 1T, and thus reducing the cost and circuit complexity.
From the foregoing description, an object of this invention is to provide a phase detecting device. The phase detecting device is used to generate a delay control signal according to a phase difference between a reference signal and a feedback signal, and then a delay control signal is fed into a counter. The counter adjusts a counting value of a counting signal according to the delay control signal so that the delay circuit generates various delay times to meet different requirements. The phase detecting device includes a phase detector, an inversion logic circuit, a latch and an OR logic circuit. The phase detector is used to generate a detected signal according the status of the feedback signal captured by the reference signal. The inversion logic circuit inverts the detected signal and outputs an inverted detected signal that is fed into the delay device to delay the inverted detected signal. The delayed inverted detected signal is then fed into the latch device. On receiving the inverted detected signal, the latch device generates a latch signal and feeds the latch signal into the OR logic circuit. The OR logic circuit further receives the detected signal. The OR logic circuit feeds the delay control signal into the counter according to the status of the detected signal and the latch signal. The counter can therefore adjust the counting signal so that the delay circuit can provide different delay time, such as T/4, T/2 or 1T, for different signal-delay requirements.